? semiconductor components industries, llc, 2006 september, 2006 ? rev. 3 1 publication order number: mc33566/d mc33566 smart voltage regulator for peripheral card applications the mc33566 low dropout regulator is designed for computer peripheral card applications complying with the instantly available requirements as specified by acpi objectives. the mc33566 permits glitch ? free transitions from ?sleep? to ?active? system modes and has internal logic circuitry to detect whether the system is being powered from the motherboard main 5.0 v power supply or the 3.3 v aux supply. the mc33566 provides a regulated output voltage of 3.3 v via either an internal low dropout 5.0 v ? to ? 3.3 v voltage regulator or an external p ? channel mosfet, depending on the operating status of the system in which the card is installed. during normal operating mode (5.0 v main supply available) the 3.3 v output is provided from the internal low dropout regulator at an output current of 0.4 a. when the motherboard enters sleep mode, the mc33566 operates from the 3.3 v aux supply and routes the aux current to the output via the external p ? channel mosfet bypass transistor controlled by the drive out pin. as a result, the output voltage provided to the peripheral card remains constant at 3.3 v even during host systems transitions to and from sleep mode. mc33566 features: ? output current up to 0.4 a ? excellent line and load regulation ? low dropout voltage ? prevents reverse current flow during sleep mode ? glitch ? free transfer from sleep mode to active mode ? compatible with instantly available pc systems figure 1. simplified block diagram v ref compensation & hysteresis +5 v in ref & detect 5v detect comp driver drive out +3.3 v out +3.3 v aux hyst sw external p?channel mosfet +3.3 v out external 4.7 f cap ldo d 2 pak d2t suffix case 936a 5 1 device package shipping ? ordering information mc33566d2t ? 1 d 2 pak 50 units/rail m5 661 awlyww 15 marking diagram a = assembly location wl = wafer lot y = year ww = work week pin 1. vaux 2. v in 3. gnd 4. v out 5. drv note: tab is ground mc33566d2t ? 1rk d 2 pak 800 tape & reel http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
mc33566 http://onsemi.com 2 pin assignments and functions pin # pin name pin description 1 +3.3 v aux auxiliary input. typical voltage 3.3 v. 2 +5.0 v in this is the input supply for the ic. typical voltage 5.0 v. (notes 1 and 2) 3 gnd logic and power ground. 4 +3.3 v out 3.3 v output provided to the application circuit (output current is sourced to this pin from the 5.0 v input.) 5 drive out this output drives a p ? channel mosfet with up to 2000 pf of ?effective? gate capacitance. recommended devices are the mmft5p03hd and mtsf1p02hd. drive out has active internal pull ? up and pull ? down circuitry to guarantee fast transitions. maximum ratings (t c = 25 c, unless otherwise noted) rating symbol value unit +5.0 v in supply voltage v in 7.0 vdc v in ? 0.5 (note 3) vdc operating ambient temperature t a ? 5.0 to +85 c operating junction temperature t j ? 5.0 to +150 c lead temperature (soldering, 10 seconds) t l 300 c storage temperature t stg ? 55 to +150 c package thermal resistance r ja (note 4) 65 c/w ac electrical specifications (notes 5, 6, and 7) characteristic symbol min typ max unit drive high delay (v in ramping up) c drive = 1.2 nf, measured from +5.0 v in = v threshi to v drive = 2.0 v t dh ? 0.5 3.5 s drive low delay (v in ramping down) c drive = 1.2 nf, measured from +5.0 v in = v threslo to v drive = 2.0 v t dl ? 0.5 3.5 s 1. see 5.0 v detect thresholds diagram. 2. recommended source impedance for 5.0 v supply: 0.12 . this will ensure that i o x r source < v hyst , thus avoiding driveout toggling during 5.0 v detect threshold transitions. 3. v in should not be allowed to go negative relative to ground. 4. mounted on recommended minimum pcb pad on fr4, 2 ? oz. copper circuit board. 5. ac specs are guaranteed by characterization, but not production tested after characterization. 6. see figure 3. application block diagram. 7. see timing diagram.
mc33566 http://onsemi.com 3 dc electrical characteristics (note 8) characteristic symbol min typ max unit +5.0 v in supply voltage range +5.0 v in 4.35 5.0 5.5 vdc reverse leakage current from output i reverse ? ? 25 a v aux quiescent current i qaux ? ? 2.0 ma +5.0 v in quiescent current, operating i qvin ? ? 10 ma load capacitance (note 9) c load 4.7 22 ? f regulator output output voltage (4.35 v v in 5.5 v, 0 ma i o 400 ma) t a = 25 c (t j = ? 5 c to 150 c) +3.3 v out 3.267 3.234 3.30 3.30 3.333 3.366 vdc in ? to ? out voltage (3.9 v v in 4.35 v, v aux = 3.3 v) v d 3.0 ? ? vdc voltage out at max voltage in (v in = 7.0 v) v outmax 3.1 3.3 3.5 vdc line regulation (i o = 400 ma) linereg ? ? 0.4 % load regulation (i o = 0 to 400 ma) loadreg ? ? 0.8 % 5.0 v detect low threshold voltage (+5.0 v in falling, i o = 400 ma) v threslo 3.9 4.05 ? vdc high threshold voltage (+5.0 v in rising, i o = 400 ma) v threshi ? 4.2 4.35 vdc hysteresis v hyst 0.05 ? ? vdc drive output output peak source current (+5.0 v in > v threshi ) i peak 15 ? ? ma output peak sink current (+5.0 v in < v threslo ) i peak 15 ? ? ma low output voltage (i ol = 200 a, v in < v threslo ) v ol ? 100 200 mvdc high output voltage (i oh = 200 a) v oh 3.4 ? ? vdc 8. ? 5 c < t a < 70 c, 4.35 v < v in < 5.5 v, c load 4.7 f unless otherwise noted. 9. 4.7 f minimum over temperature; 22 f recommended; 500 m esr maximum.
mc33566 http://onsemi.com 4 v ref compensation & hysteresis +5 v in ref & detect 5v detect comp driver drive out +3.3 v out +3.3 v aux hyst sw external p?channel mosfet +3.3 v out external 4.7 f cap ldo figure 2. functional block diagram functional description input blocking ? the internal npn pass transistor of the ldo regulator ensures that no significant reverse current will flow from +3.3 v out back to the +5.0 v in input when the 5.0 v input is not powered and the 3.3 v in supply is present. 5.0 volt detect ? internal circuitry detects the presence of the 5.0 v input supply. when the 5.0 v supply drops below a given threshold, the +3.3 v in bypass transistor (an external p ? channel mosfet) is enabled. the 5.0 v detect logic is active throughout the entire range of ramp ? up from 0 to 5.5 v. additionally, the drive out signal is never turned on or off inappropriately during ramp ? up of the +5.0 v in supply. also, +3.3 v out never drops below 3.0 v while +5.0 v in is above the 5.0 v detect minimum threshold. glitch ? free transfer ? the design of the 5.0 v detect circuitry and drive out control circuitry guarantees that the +3.3 v out will not exceed the output voltage specification listed in the table of dc operating specifications even with +5.0 v in ramping up and down at the extremes of the slew rates in the table of ac operating specifications. offset voltage performance ? to ensure performance when external offsets are present on the +5.0 v in and +3.3 v in power inputs, the device has been designed to be capable of operating with either one or both of these inputs rising from or falling to zero volts, or with offsets of 0.05 v to 0.9 v as the inputs ramp up and down. motherboard/ mainboard pci slot figure 3. application block diagram pci card circuitry 5v 3.3v aux 4.7 f 1 2 3 4 5 d r v o g n d v i n v a u x 4.7 f
mc33566 http://onsemi.com 5 figure 4. 5.0 v detect thresholds diagram vin 3.8v v th(hi) figure 5. timing diagram 4.4v 2.0v 2.0v v th(lo) v hyst dr vin 3.8v 4.4v 2.0v 2.0v dr t dh t dl note: (1) v in rise and fall times (10% to 90%) to be 100 s. note: (1) v in rise and fall times (10% to 90%) to be 100 ns. figure 6. predicted gain and phase at zero load current figure 7. predicted gain and phase at full load current or gain (db) 0 frequency (hz) 100 200 phase margin 10 1 10 3 10 5 v out capacitor 5 f 20m esr note: v out capacitor 4.7 f over operating temperature range. maximum esr permissable = 500 m over operating temperature range. phase margin gain db or gain (db) 0 frequency (hz) 100 200 phase margin 10 1 10 3 10 5 v out capacitor 5 f 20m esr phase margin gain db
mc33566 http://onsemi.com 6 package dimensions (d 2 pak) d2t suffix plastic package case 936a ? 02 issue b 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 mc33566/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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